Sitao Huang (黄思陶)

sitaoh [AT] uci [DOT] edu

Assistant Professor
Department of Electrical Engineering and Computer Science
University of California Irvine

I am an assistant professor at University of California Irvine EECS. I got my a Ph.D. degree in Electrical and Computer Engineering at UIUC in August 2021. During my PhD, I worked in IMPACT research group and ES-CAD research group at UIUC. I was fortunate to be advised by Professor Wen-mei W. Hwu and Professor Deming Chen.

My research interests include FPGA/GPU based heterogeneous computing, high level synthesis (HLS), and compiler technologies.

My CV can be found here.

[NEWS] I am recruiting Fall 2022 students at UC Irvine EECS. Please contact me if you are interested.

Sitao Huang

Education


Teaching


Honors


Selected Research Projects


PyLog Flow

PyLog: A High-Level Programming and Synthesis Flow for FPGAs

PyLog is a high-level, Python-based algorithm-centric programming and synthesis flow for FPGA. PyLog features a set of compiler optimization passes and a type inference system to generate high-quality design.

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Auto-Quantization Flow for ReRAM DNN Accelerators
Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators
(ASP-DAC 2021 Best Paper Candidate)

We propose a mixed precision quantization scheme for ReRAM-based DNN inference accelerators where weight quantization, input quantization, and partial sum quantization (ADC quantization) are jointly applied for each DNN layer. We also propose an automated quantization flow powered by deep reinforcement learning to search for the best quantization configuration in the large design space.

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Chai-FPGA: Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures

Chai-FPGA: Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures

We propose the collaborative schemes for CPU-FPGA systems, including data partitioning, coarse-grained task partitioning, and fine-grained task partitioning. We explore and evaluate the potential of collaborative execution between CPUs and FPGAs using OpenCL high level synthesis. We observe that choosing the most suitable partitioning strategy can improve performance by up to 2x.

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Tangram: A High-Level Language for Efficient Performance-Portable Kernel Synthesis

Tangram: A High-Level Language for Efficient Performance-Portable Kernel Synthesis

Tangram is a general-purpose high-level language that achieves high performance across architectures, including GPUs and multi-core CPUs. In Tangram, a program is written by synthesizing elemental pieces of code snippets, called codelets. A codelet can have multiple semantic-preserving implementations to enable automated algorithm and implementation selection. An implementation of a codelet can be written with tunable knobs to allow architecture-specific parameterization. The Tangram compiler produces highly optimized code by choosing and composing architecture-friendly codelets, and then tuning the knobs for the target architecture.

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Internships


Publications


Last updated in January 2021